Fault coverage testing on the ISCAS’89 S1423 sequential circuit using scan based design and synopsis tetramax

Wirmanto, Suteddy and Anugrah, Adiwilaga and Dastin, Aryo Atmanto (2022) Fault coverage testing on the ISCAS’89 S1423 sequential circuit using scan based design and synopsis tetramax. Journal of Computer Engineering, Electronics and Information Technology, 1 (1): 5. pp. 32-41. ISSN 2829-4157

[thumbnail of Jurnal COELITE_Wirmanto Suteddy_Universitas Pendidikan Indonesia_2022_5.pdf]
Jurnal COELITE_Wirmanto Suteddy_Universitas Pendidikan Indonesia_2022_5.pdf - Published Version
Available under License Creative Commons Attribution Non-commercial Share Alike.

Download (849kB) | Preview


We tested the ISCAS'89 S1423 series with a scan design method, both non scan, full-scan, and partial-scan, but for the partial-scan, the method we propose uses a structured random approach. The purpose of this study is to determine the evaluation and performance with the best computational time with the proposed method to produce high fault coverage results. Testing the ISCAS'89 S1423 circuit in the form of verilog was carried out using tetramax synopsis, the partial-scan test requires a strategy in determining the flip flop to be used as a scannable flip flop, the test results using the full scan method produce 100% test coverage and fault coverage, but this method provides gate overhead loss of 24.06% and slower chip performance. To reduce the gate overhead loss, a partial-scan method will be applied with the approach of choosing from 74 DFF which will be used as scannable flip flops, the test with the best results we did through the 37 DFF approach with the highest input obtained test coverage of 98.17% and fault coverage 96.76% with 171.11 CPU Time with gate overhead reduced by 12.03%. The next approach with the best results with the approach of 50 DFF highest output plus DFF which is not self-loop obtained test coverage of 99.24% and fault coverage of 98.47% with gate overhead successfully reduced by 16.26% with CPU Time 43.39.

Item Type: Article
Uncontrolled Keywords: S1423, Sequential circuit, Tetramax, Design for testability, Fault coverage VLSI
Subjects: Computers, Control & Information Theory > Computer Hardware
Computers, Control & Information Theory > Applications Software
Depositing User: Syifa Naufal Qisty
Date Deposited: 27 Mar 2023 05:19
Last Modified: 27 Mar 2023 05:19
URI: https://karya.brin.go.id/id/eprint/15090

Actions (login required)

View Item
View Item